Debugging

VCLK

This is the clock signal of the 68k CPU
The image shows the typical waveform and phase relationship relative to the master clock MCLK.
The VCLK edge occurs 12ns after the corresponding edge of MCLK.
This waveform and phase are recommended for Megaswitch HD.

EDCLK

This is the External Dot Clock.
The image shows two versions of the signal: EDCLK after the ferrite bead (as in VA4 revision) and the raw EDCLK signal (as in VA2 revision).
As you can see, the ferrite bead causes waveform smoothing and introduces a 15ns phase shift.
This is not acceptable for Megaswitch HD.
Therefore, in VA4 revision, it is recommended to tap EDCLK before the ferrite bead (as shown in the lower blue waveform).

ZCLK

This is the clock signal of the Z80 processor.
The figure shows the ZCLK signal relative to the master clock MCLK.
The typical and recommended phase offset is 4ns.
With this waveform and phase relationship, stable operation of MegaSwitch HD is achieved.
Thermal stability is also ensured.

ZCLK (Non-Recommended Phase)

On the VA4 revision, capacitor C88 shifts the signal phase by 14ns.
This results in artifacts on Megaswitch HD when operating in Master System mode.
It is recommended to remove capacitor C88.

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